• Intel
  • $106,005.00 -167,990.00/year*
  • Austin , TX
  • Electronics/Semiconductors
  • Full-Time
  • 5006 Emma Browning Ave

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Physical Design EngineerJob Description

Become a key member of a team participating in the design of Atom CPUs. We are looking for talented individuals to be part of a high performing team in the physical design of highly complex blocks from synthesis/APR through post-layout verification and tapeout. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

The ideal candidate should exhibit the following behavioral traits:

Problem-solving skills

Ability to multitask

Strong written and verbal communication skills

Ability to work in a dynamic and team oriented environment

We are looking for a talented individual to drive implementation of standard cell-based design (CBD) blocks from synthesis through post-layout verification and tapeout. You will develop the custom constraints for driving synthesis and Auto-Place and Route (APR) tools to implement and optimize the design. You will work closely with the micro-architecture, RTL and custom circuit teams to converge the design to project targets.


You must possess the below minimum qualifications to be initially considered for the position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

You must possess a Bachelors in Electrical Engineering or Computer Engineering or equivalent with 3+ years experience.

Experience with:

* Synthesis, APR and timing tools and flows
* Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
* Unix or Linux, Perl and TCL coding.

Preferred Qualifications:

* 3 or more years of industry experience/exposure with CPU Micro-Architecture
* Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution.
* Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques.
* Strong knowledge of RTL2GDS methodologies and formal equivalence.
* Familiar with Synopsys tool suite (DC, ICC2, PrimeTime)

Inside this Business Group

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

Associated topics: architecture, asic, cadence, catia, design, engg, engineer, engineer i, pcb, schema

* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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