• New York Technology Partners
  • $104,670.00 -157,460.00/year*
  • Austin , TX
  • Engineering
  • Full-Time
  • 1604 Chippeway Ln

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Expert in Synthesis to Tape-out flow, including Layout, DFT, Timing Closure, and Chip Finishing Ability to independently handle complex blocks to closure right from Synthesis Worked on at least 2 end to end projects those spanned across entire life cycle of development Ability to communicate with architecture, RTL design and other remote teams Excellent verbal and written communication skills Preferably experience in 20 nm, 14 nm flows Performing a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization, Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), Timing closure (STA), DRC, LVS, Antenna checks, IR drop (RedHawk), multi voltage checks etc. Participating in the development of a back-end SoC design flow. Experience of UPF low power design through synthesis, place and route. Expertise in Synopsys suite (IC Compiler, Primetime, Design Compiler) Excellent people leadership skills, ability to leadcoordinate mult-site projects, strong communication and influencing skills required
Associated topics: assembly language, bsee, circuit, computer engineer, electronic, etch, embedded, gpu, pcb, robot

* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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